RTL Design Engineer, Security

Minimum qualifications:

• 5 years of experience in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC).
  
• Experience in scripting language such as Perl or Python.
  
• Experience in area, power and performance optimization.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
• Experience in design and development of security blocks or crypto blocks.
  

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes Micro architecture, RTL coding, UPF definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews and closure for high quality and optimized security designs.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Participate in test planning and coverage analysis.
  
• Develop RTL implementations that meet power, performance and area goals.
  
• Participate in synthesis, timing/power closure and 
  Field Programmable Gate Array (FPGA) and silicon bring-up.
  
• Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks.
• Create tools/scripts to automate tasks and track progress.
  

Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks.Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks.Create tools/scripts to automate tasks and track progress.Create tools/scripts to automate tasks and track progress.